Active Serial (AS) configuration of Cyclone® V devices may be seen to fail with EPCQA devices at low temperatures (< 20 degree C and below) due to a hold timing issue.
Cyclone V AS configuration’s minimum data hold time(tDH) spec has been revised as below :
- 2.5ns – For -6 speed grade
- 2.9ns – For -7 and -8 speed grade
- Calculate the hold time required for Active Serial configuration scheme, as mentioned in the 'Evaluating Data Setup and Hold Timing Slack' section of AN822 to evaluate the hold time slack on the board.
- Select a flash memory device with larger min tCLQX value as per the 3rd party flash datasheet.
- For example, you can obtain 2ns tDH slack by using any of the following 3rd party flash devices
- Winbond™ W25Q-FV
- Cypress™ S25FL-S/S70FL-S/S25FL1-K
- Macronix™ MX25L6445E/MX25L6465E/MX25L12845E/MX25L12865E/MX25L25635E
- Add a series termination resistor / buffer / capacitor on DCLK and AS_DATA[3:0] traces to increase the propagation delay on the respective signals.
- An IBIS/link simulation is highly recommended to derive the extra delay expected to meet the tDH requirement, to ensure the signal integrity is good and to ensure the flash device's input timing specification is met.