Article ID: 000086599 Content Type: Troubleshooting Last Reviewed: 01/20/2023

Is there an issue with Configuration via Protocol (CvP) when configuring using CvP with truncated or corrupted periphery/core bitstream in Intel® Agilex™ P-Tile, R-Tile, and F-Tile devices?

Environment

  • Intel® Quartus® Prime Pro Edition
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    Description

    In Intel® Quartus® Prime Pro Edition Software version 21.2 and below, performing CvP configuration can cause the Intel® Agilex™ P-Tile, F-Tile, and R-Tile devices to hang if a truncated or corrupted periphery/core bitstream is sent.

    Once the FPGA hangs due to receiving a truncated or corrupted periphery/core bitstream, subsequent reconfiguration via CvP Initialization Mode/CvP Update Mode cannot be performed.

     

     

    Resolution

    This problem is already fixed in Intel® Quartus® Prime Pro Edition Software version 22.2.

    Related Products

    This article applies to 2 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs I-Series
    Intel® Agilex™ 7 FPGAs and SoC FPGAs F-Series

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