Description
This error may be seen when trying to compile an Arria® V GZ or Stratix® V Hard IP for PCI Express® for the Avalon® Memory Mapped Qsys component in VHDL.
This problem is due to a Verilog HDL to VHDL conversion issue.
Resolution
Comment out the two offending tlbfm_out occurences from the top level wrapper in the file that is calling the altpcie_sv_hip_avmm_hwtcl component .
This problem is scheduled to be fixed in a future version of the Quartus® II software.