Why does the FPGA to HPS bridge address width dropdown in the Hard Processor System Intel® Stratix® 10 FPGA IP allow for up to 40-bit addressing?

The Bridge Address width dropdown in the FPGA to HPS slave interface section of the HPS FPGA AXI Bridges section on the FPGA Interfaces tab of the Hard Processor System Intel Stratix 10 FPGA IP allows selections of up to 40-bit addressing.  However, the HPS address map as visible from the FPGA is only 128GB, or 37-bits.

In the Stratix 10 HPS interconnect, the high order bits are available but ignored.  Masters accessing this bridge should not use these bits.

This is scheduled to be fixed in a future version of the Intel® Quartus® Prime Pro Software.