Article ID: 000086464 Content Type: Troubleshooting Last Reviewed: 01/26/2018

cv_5v4 Cyclone V Hard Processor System Technical Reference Manual --> Errata

Environment

  • Intel® Quartus® Prime Pro Edition
  • Arria® V Cyclone® V Hard Processor System Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    In version 2018.01.26 of cv_5v4 Cyclone V Hard Processor System Technical Reference Manual, page 22-53 incorrectly show cpr register bits 23:16 description and reset value. The correct reset value of these bits is 0x08, representing FIFO Depth of 128 bytes.

    This error will be corrected in future release of the technical reference manual.

     

    Related Products

    This article applies to 1 products

    Cyclone® V FPGAs and SoC FPGAs

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