Article ID: 000086463 Content Type: Troubleshooting Last Reviewed: 01/22/2018

Why does the Remote Update IP core not able to read current remote update settings in Intel® Arria® 10 devices?


  • Remote Update Intel® FPGA IP

    A new port named ctl_nupdt has been introduced in Intel® Arria® 10 devices. This port allows you to select either Control/Update register to be read whenever read_param operation is running. This port is defaulted to logic low which selects the Update Register.

    Control Register contains the current remote update settings such as watchdog timer settings, configuration mode (AnF) and page address. Update Register contains similar data as held in the Control Register, but the values are updated via write_param operation for use in next reconfiguration.


    For Remote Update IP core without Avalon®-MM interface, set ctl_nupdt port to logic high which selects the Control Register. 

    For Remote Update IP core with Avalon®-MM interface, set RU_CTL_NUPDT register to logic 1 to allow capturing of data from Control Register.

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs