You might receive critical warning messages similar to the one shown below, when compiling the Viterbi Intel® FPGA IP.
Critical Warning (15003): "mixed_port_feed_through_mode" parameter of RAM atom auk_vit_par_top_atl:auk_vit_par_top_atl_inst|auk_vit_par_trb_atl:\ifg_cont:tracing_back_cont|altsyncram:stop_RAM|altsyncram_8j83:auto_generated|ram_block1a22 cannot have value "old" when different read and write clocks are used.
The reason you are getting these critical warning messages is due to the configuration of the RAM used by the core. As indicated in the warning message, the configuration of the RAM used by the core is read_during_write=old data. This is indicating that when you are writing to the same location you are reading from, the RAM will provide the old data value.
The Viterbi Intel FPGA IP core is designed so that it is not reading from and writing to the same address at the same time so the design is safe to use.
Due to the design of the Viterbi Intel FPGA IP core, it is safe to ignore these critical warning.
This problem will be fixed in a future release of the Quartus® II software.