Due to advanced and high density serial flash devices that can operate in modes（three-byte/four-byte addressing mode）more capable than the common configuration that is assumed by three-byte addressing mode, the Intel® Cyclone ® V HPS will hang when configure the HPS cold reset register(0xffd05004) through the UBOOT command “mw 0xffd05004 0x00110001” without resetting QSPI flash to three-byte addressing mode. The UART print as below:
CPU: Altera SOCFPGA Platform
BOARD: Altera SOCFPGA Cyclone V Board
I2C: ready
DRAM: 1GiB
MMC: ALTERA DWMMC: 0
SF: Read data capture delay calibrated to 3 (0- 7)
SF: Detected N25Q512 with page size 65536, total: 67108864
*** Warning - bad CRC, using default environment
In: serial
Out: serial
Err: serial
Net: mii0
Hit any key to stop autoboot: 0
SOCFPGA_CYCLONE5 #
SOCFPGA_CYCLONE5 # mw 0xffd05004 0x00110001
You can set the QSPI in three-byte address mode before configuring the HPS cold reset register(0xffd05004) or output the h2f_cold_reset from FPGA pin to reset the QSPI Flash to three-byte address mode.