Article ID: 000086341 Content Type: Troubleshooting Last Reviewed: 10/20/2021

Why do I see functional errors in hardware when using the Intel® Stratix® 10 10GBASE-KR PHY IP core?

Environment

  • Intel® Stratix® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • 10GBASE-R PHY Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software versions 20.1 and later, you may see hardware failures when using the Intel® Stratix® 10 10GBASE-KR PHY IP core. 

    This problem occurs because of incorrect timing constraints in the auto-generated Intel® Stratix® 10 10GBASE-KR PHY IP core Synopsys Design Constraint (SDC) file. The paths to the xgmii_tx_dc input of the IP or from the xgmii_rx_dc output of the IP may be incorrectly constrained. This problem may occur even if no timing violations are reported in the Timing Analyzer. 

    Only intellectual property (IP) implementations with the following clocking topologies are impacted by this problem:

        • The xgmii_tx_clk port of the IP and the clock feeding the logic or MAC driving the xgmii_tx_dc port of the IP are both connected to the same externally-generated clock

        • The xgmii_rx_clk port of the IP and the clock feeding the logic fed by the xgmii_rx_dc port of the IP are both connected to the same externally-generated clock

    If your design uses the clocking topology listed above and is still in development, see the Resolution section for corrective action.  For designs already in production that use the clocking topology listed above, follow these steps to see if any timing violations exist for a precompiled design:

    1. Locate the original auto-generated 10GBASE-KR PHY sdc file: \\altera_xcvr_10gkr_s10_\synth\altera_xcvr_10gkr_s10_.sdc.
    2. Rename this file to:\\altera_xcvr_10gkr_s10_\synth\altera_xcvr_10gkr_s10__original.sdc.
    3. Copy the corrected-krphy-sdc-to-rename.sdc file at the following link (corrected-krphy-sdc-to-rename.sdc) into the same location, and then rename it to the same name as the original .sdc file (the "altera_xcvr_10gkr_s10_.sdc" name prior to the modification in step 2).
    4. Re-run the timing analysis for the project and check for violations. 

           Note: The auto-generated .sdc file will be overwritten if the IP is regenerated so these steps will need to be repeated if the IP is regenerated.  

    Resolution

     

    If your design is impacted and you are using the Intel® Quartus® Prime Pro Edition Software versions 20.3 or 21.2, download and install the relevant patch from the following list:

    Note: For the patch to take effect, the 10GBASE-KR PHY IP core must be regenerated after installing the patch. 

    If you are using Intel® Quartus® Prime Pro Edition Software versions 20.1, 20.2, 20.4, or 21.1, upgrade to the software patch v21.2 and install Patch 0.07.

    This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software v21.3.

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