Article ID: 000086269 Content Type: Troubleshooting Last Reviewed: 08/24/2017

Why does a10_ref BSP compile show several unconstrained paths?

Environment

  • Intel® Arria® 10 GX FPGA
  • Intel® Quartus® Prime Pro Edition
  • Intel® FPGA SDK for OpenCL™
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    In the Intel® FPGA SDK for OpenCL™ 17.0 BSP flow, you may see several paths or clocks remain unconstrainted.

    Resolution

    Users will need to comment out or remove the following lines in their top.qsf file:

    # base revision compile SDC constraints only

    set_global_assignment -name SDC_FILE base.sdc

    set_global_assignment -disable -name SDC_FILE top.sdc

    set_global_assignment -disable -name SDC_FILE top_post.sdc

     

    It will be required to do another import compile after changing the QSF file

    aoc --board <BSP_name> <kernel_name>.cl 

    This problem is scheduled to be fixed in a future release of the Intel® FPGA SDK for OpenCL™.

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