Article ID: 000086268 Content Type: Troubleshooting Last Reviewed: 06/13/2017

Why is the MPU clock frequency on my DE10-Nano SoC system set so low?

Environment

  • Intel® Quartus® Prime Pro Edition
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    Description

    Due to a problem in the Quartus® Prime Standard software version 17.0 and earlier, the MPU clock frequency may be incorrectly set if the use default option is selected with the 5CSEBA6U2317DK device  specified.

    If the use default option is selected on the Output clocks tab of the HPS IP Parameter editor, the MPU clock rate may be set to 0.

    Resolution

    To work around this problem in the Quartus Prime Standard software versions 17.0 and earlier:

    1. Open the output clocks page of the HPS IP parameter editor in Qsys.
    2. Un-tick the use default MPU clock setting
    3. Manually set the MPU clock rate to 800 in the MPU Clock box
    4. Re-generate the Qsys system
    5. Re-compile the Quartus Prime project
    6. Generate a new Pre-loader using BSP-Editor

    This problem is scheduled to be fixed in a future release of the Quartus Prime Standard software.

    Related Products

    This article applies to 3 products

    Cyclone® V SE SoC FPGA
    Cyclone® V ST SoC FPGA
    Cyclone® V SX SoC FPGA

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