Article ID: 000086266 Content Type: Troubleshooting Last Reviewed: 03/22/2022

Why does my Intel® Stratix® 10 SoC design sometimes fail to detect a transition on hps_cold_nReset ?


  • Intel® Quartus® Prime Pro Edition

    Due to problem in the Intel® Stratix® 10 Device Datasheet, the pulse width requirement on the Intel Stratix 10 FPGA SDM HPS_cold_nReset pin is not documented. 


    The pulse width requirement on the hps_cold_nReset pin is 3 ms.


    • It is not required to cold reset the HPS if the intention is to reconfigure the device using the nConfig signal.  An nConfig event (reconfiguration) will wipe the entire device (HPS and FPGA), and then reconfigure the device from the selected boot device (MSEL setting).
    •  nConfig must not be issued when an HPS reset in process. If there is a HPS reset in process,  wait for the HPS reset to finish before issuing nConfig: Greater than 10 ms from time HPS reset is triggered.

    Also see :  Why does my Intel Stratix 10 SoC device fail to boot or configure correctly, if I reset the HPS while a configuration event is taking place? 

    This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 20.3.

    Related Products

    This article applies to 3 products

    Intel® Stratix® 10 SX SoC FPGA
    Intel® Stratix® 10 MX FPGA
    Intel® Stratix® 10 TX FPGA