How can I enable timing analysis of the HPS Ethernet interfaces via the FPGA?

Timing analysis of the HPS Ethernet interfaces via the FPGA is disabled by default.  It can be enabled on Cyclone® V SoC and Arria® V SoC by following the steps below.

To enable timing analysis in the Quartus® Prime Standard edition software for HPS Ethernet interfaces via the FPGA add the following global assignment in the Quartus Settings File (.qsf) for your project

               set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING ON

Notes:  

• Users must ensure the external interfaces on the FPGA are constrained
  • For details on constraining RGMI Iinterfaces please see: https://www.altera.com/support/support-resources/design-examples/intellectual-property/exm-tse-rgmii-phy.html
• This global assignment replaces the quartus.ini variable used in the RGMII and SGMII examples on Rocketboards.org
  
• From the Quartus II software version 15.1 QSYS will add constraints for the HPS EMAC to FPGA fabric interface. 

This information is scheduled to be included in a future release of the Cyclone V SoC and Arria V SoC Technical Reference Manuals