Article ID: 000086168 Content Type: Product Information & Documentation Last Reviewed: 08/30/2017

How can I enable timing analysis of the HPS Ethernet interfaces via the FPGA?

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Timing analysis of the HPS Ethernet interfaces via the FPGA is disabled by default.  It can be enabled on Cyclone® V SoC and Arria® V SoC by following the steps below.

     

    Resolution

    To enable timing analysis in the Quartus® Prime Standard edition software for HPS Ethernet interfaces via the FPGA add the following global assignment in the Quartus Settings File (.qsf) for your project

                   set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING ON

    Notes:  

    This information is scheduled to be included in a future release of the Cyclone V SoC and Arria V SoC Technical Reference Manuals

    Related Products

    This article applies to 5 products

    Cyclone® V SE SoC FPGA
    Cyclone® V ST SoC FPGA
    Cyclone® V SX SoC FPGA
    Arria® V SX SoC FPGA
    Arria® V ST SoC FPGA

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