Article ID: 000086167 Content Type: Troubleshooting Last Reviewed: 08/30/2017

Why does my Arria 10 SX device fail to boot if the HPS is reset while configuring the FPGA or performing AES decryption?


  • Intel® Quartus® Prime Pro Edition

    Critical Issue


    The Arria® 10 SX device may hang if the HPS has control over the CSS block (performing configuration, PR, or AES decryption) and receives a cold or warm reset before it relinquishes control.  The problem occurs in this situation because the HPS retains control over the CSS block after the reset, but another source needs control over the CSS block to perform the requested function, such as if the JTAG is attempting to configure the FPGA or if nCONFIG is asserted for reconfiguration. Note that if you are using secure boot, you are not affected by this issue as the HPS Boot ROM code automatically relinquishes control of the CSS.


    If this situation occurs, normal operation can be resumed by performing a Power on reset (POR), cold reset or warm reset of the HPS, which causes the HPS to relinquish control of the CSS and gives control back to the FPGA.    If you are not using secure boot, you can avoid this issue by ensuring that software executing after the boot ROM stage relinquishes HPS control of the CSS after a reset to let the FPGA proceed to take ownership of the CSS block.  It is important that the HPS is not held in cold or warm reset indefinitely, otherwise the CSS will not be accessible to FPGA configuration sources.

    This information is scheduled to be included in a future release of the Arria 10 Technical Referenece Manual.


    Related Products

    This article applies to 2 products

    Intel® Arria® 10 SX SoC FPGA
    Intel® Arria® 10 FPGAs and SoC FPGAs