Article ID: 000086072 Content Type: Troubleshooting Last Reviewed: 04/21/2021

Why does my eSRAM Intel® Agilex™ FPGA IP not meet the maximum performance specification?

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition software version 19.3 and later, the eSRAM Intel® Agilex™ FPGA IP may not meet the maximum performance specification due to a hold violation.

    Resolution

    To work around this problem, modify the design file by adding  “ (* altera_attribute = "-name HYPER_REGISTER_DELAY_CHAIN 100"*) ” to the eSRAM IP instance. 

    For Example:

    (* altera_attribute = "-name HYPER_REGISTER_DELAY_CHAIN 100"*) esram esram_inst(       
            .esram0_ram_input_clk          (clk_500),
            ......

    This problem is fixed starting with the Intel® Quartus® Prime Pro Edition software version 21.2.

    Related Products

    This article applies to 1 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs

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