Article ID: 000086061 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why am I getting a fitting error for Stratix II devices using DPA channels in more than 25 rows in Quartus II software versions 5.0 and later?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description The DPA clock tree in Stratix® II devices will only support the channels in the first 25 rows adjacent to the PLL
that is feeding the DPA bank. Versions prior to Quartus II version 5.0 did not check for this rule. Quartus II version 5.0 and later will give a
fitting error if any LVDS channel with DPA is over 25 rows away from the PLL that is driving it.

The solution is to make sure that the DPA channels is within 25 rows from the PLL that's driving it.

Related Products

This article applies to 1 products

Stratix® II FPGAs

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