Article ID: 000085941 Content Type: Error Messages Last Reviewed: 09/11/2012

Error: I/O standard assignment 3.0-V LVCMOS to pin is not supported by device



You will receive this error message when compiling a design using a Stratix® IV device in Quartus® II software that was originally created targeting a Stratix III device. Device migration is possible between Stratix III and Stratix IV E devices. However, one of the differences you need to be aware of is how 3.3V LVTTL and 3.3V LVCMOS I/O standards are defined between these two device families.

Stratix III devices support LVTTL and LVCMOS I/O standards with both a 3.0V VCCIO and a 3.3V VCCIO. You can select either "3.3-V LVTTL / LVCMOS" or "3.0-V LVTTL / LVCMOS" as I/O standards in Stratix III devices, and the VCCIO will be set according to the 3.3-V or 3.0-V I/O standard selections. In order to be compatible with Stratix IV devices which do not support a 3.3V VCCIO, you would have to select "3.0-V LVTTL / LVCMOS" I/O standards in your design targeting a Stratix III device if you planned for Stratix IV E migration.

To be consistent with JEDEC naming conventions, Stratix IV devices allow you to select "3.3-V LVTTL / LVCMOS" as the I/O standard in Quartus II software, there is no selection for "3.0-V LVTTL / LVCMOS". Stratix IV devices are compatible with 3.3V LVTTL and 3.3V LVCMOS I/O standards using a 3.0V VCCIO. If you are migrating a design from a Stratix III device to a Stratix IV E device, you will need to change all I/O standards which use "3.0-V LVTTL / LVCMOS" to "3.3-V LVTTL / LVCMOS" so the design can successfully compile in the Stratix IV E device.

Related Products

This article applies to 3 products

Stratix® IV GT FPGA
Stratix® IV GX FPGA
Stratix® IV E FPGA