Article ID: 000085929 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Are there any known issues when the Stratix Fast PLL is used in the no-compensation mode?


Description When using the Fast PLL in no-compensation mode in Quartus II versions 4.0 and earlier, the compiler incorrectly phase shifts the output clock from the PLL to compensate for the clock network delays. This is incorrect behavior, as there should be no delay compensation in this mode. This problem is fixed in Quartus II v4.0 SP1. To ensure consistent tSU/tCO numbers when migrating to other Stratix family devices, please use 4.0 SP1. If you want to maintain the same timing relationships after upgrading to Quartus II 4.0 SP1, use the phase shift feature of the PLL to shift the clock edge back to its original position. You can also use this same technique for getting 4.0 SP1 tSU/tCO times in pre-4.0 SP1 versions.

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Stratix® FPGAs