If your Arria® 10 memory controller IP has the MMR interface enabled, you may notice that the mmr_readdatavalid signal asserts occasionally even when no read commands are issued.
The mmr_readdatavalid assertion originates from the memory controller\'s internal read command and could cause the Avalon Master to capture the wrong read data.
The Avalon Master must only accept mmr_readdatavalid based on the following requirement:
mmr_readdatavalid returns 1 cycle after issuing read request to MMR register ecc1, ecc2, ecc3, ecc4.
mmr_readdatavalid returns 3 cycles after issuing read request to all other MMR registers other than ecc1, ecc2, ecc3, ecc4.
Example: The Avalon Master should only accept mmr_readdatavalid one clock cycle after sending read request to register ecc1 (with mmr_waitrequest signal low).