Due to a problem in the Quartus® II software version 12.1 and later, you may see this error in Stratix® V devices when using the ALTLVDS_RX megafunction in external PLL mode.
Error: SERDES receiver node 'lvds_rx:lvds_rx_inst0|altlvds_rx:ALTLVDS_RX_component|lvds_rx_lvds_rx:auto_generated|rx_0' is not properly connected on the 'CLOCK0' port. It must be connected to one of the valid ports listed below.Info: Can be connected to LVDSCLK port of stratixv_pll_lvds_output WYSIWYGInfo: Can be connected to OUTCLK port of generic_pll WYSIWYG
To workaround this problem an LVDS buffer needs to be inserted between the external pll and the ALTLVDS instance on the rx_inclock and the rx_enable ports.
Refer to the related solution below to learn how you can add an intermediate LVDS buffer between the external PLL and ALTLVDS IP.
