Article ID: 000085799 Content Type: Troubleshooting Last Reviewed: 08/27/2013

Why do I see an offset between the input and output clocks for Stratix III device PLLs operating in zero delay buffer compensation mode?



You may see an offset between the input and output clocks when running a Stratix® III device PLL in zero delay buffer (ZDB) compensation mode if your project is compiled in the Quartus® II software version 8.0 SP1 or any previous version.

ZDB compensation mode aligns the rising edge of the clock at the dedicated input pin of a PLL to the rising edge of the output clock at the dedicated output pin of the PLL.  However, the compensation delays were not optimized in Quartus II software versions prior to 8.1.

The compensation delays were fixed beginning in version 8.1 of the Quartus II software.  This is also the first version with final timing models for specific device densities in the Stratix III family. 

If you cannot upgrade your version of the Quartus II software to a version with the fixed compensation delays, you can add a phase shift in the ALTPLL megafunction to compensate for the clock offset.  You should measure the offset on your board to determine the value for the necessary phase shift.

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Stratix® III FPGAs