Article ID: 000085793 Content Type: Error Messages Last Reviewed: 12/01/2012

Error When Simulating DDR3 with Ping Pong PHY Using VHDL and ModelSim

Environment

    Quartus® II Subscription Edition
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Critical Issue

Description

This problem affects DDR3 products.

A simulation error can occur when you simulate a quarter-rate DDR3 design using VHDL and ModelSim, with Ping Pong PHY enabled and the calibration mode set to Quick or Full.

Resolution

The workaround for this issue is to do one of the following: set the calibration mode to Skip; use Verilog instead of VHDL; or use a different simulator.

This issue will be fixed in a future release.

Related Products

This article applies to 1 products

Intel® Programmable Devices

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