Article ID: 000085780 Content Type: Troubleshooting Last Reviewed: 10/12/2016

Can I disable the HPS warm reset handling code in Preloader?

Environment

  • Quartus® II Subscription Edition
  • Reset
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Yes, the warm reset handling code can be disabled in the Preloader, if any of the following conditions is met:

    1. CSEL is set to 01, 10 or 11 and a fixed revision of the silicon is used.
    2. HPS cold and warm reset pins are tied together.
    3. BSEL is set to boot from FPGA.

     For more information on the warm reset handling code patch see the related solution below.

     


     

    Resolution

     

    To disable the code follow the steps below:

    1. Edit the file uboot-socfpga\arch\arm\cpu\armv7\socfpga\spl.c to remove the call of the function ram_boot_setup(). This eliminates the restriction on the upper 4KB of OCRAM, which will now be available for the user.
    2. Recompile the Preloader.

    Note: The Preloader does not behave differently on different silicon revisions of the SoC devices. This solution is applicable for all versions of silicon, including the ones where the HPS PLL lock issue is fixed.

    For more information about the fixed silicon revisions, refer to the device errata sheet.

     

     

    Related Products

    This article applies to 5 products

    Cyclone® V SX SoC FPGA
    Arria® V ST SoC FPGA
    Arria® V SX SoC FPGA
    Cyclone® V SE SoC FPGA
    Cyclone® V ST SoC FPGA

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.