Article ID: 000085704 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why is control logic for counters generated incorrectly in the Quartus® II software versions 4.1 and 4.1 SP1?


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    Control logic is incorrectly generated due to a problem in the Quartus II software versions 4.1 and 4.1 SP1 if the following conditions are met:

    • You instantiate an lpm_counter megafunction or the lpm_counter megafunction is inferred from your HDL code during synthesis
    • The counter in your design uses both asynchronous preset and synchronous clear signals
    • You compile the design targeting Stratix®, Stratix GX, Cyclone®, MAX® II, or Hardcopy Stratix devices

    The incorrect behavior is due to a problem with the clear box implementation of the lpm_counter megafunction. To avoid the problem if you have a counter in your design that uses both the asynchronous preset and synchronous clear signals, copy the lpm_counter.tdf file from the <Quartus II installation directory>\libraries\megafunctions directory to your project directory.

    This problem is fixed beginning with the Quartus II software version 4.2.

    The following is an example of code that is implemented incorrectly in the Quartus II software versions 4.1 and 4.1 SP1. In this example, the clr signal is removed in the final implementation.

    process (clk, clr, preset) is
       if (preset = '0') then
          counter <= (others => '1');
       elsif rising_edge(clk) then
          if (clr = '1') then
             counter <= (others => '0');
         counter <= counter   1;
          end if;
       end if;
    end process;

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    Stratix® FPGAs