Article ID: 000085664 Content Type: Troubleshooting Last Reviewed: 03/04/2015

Can I set test_in ports of Arria II, Cyclone IV, and Stratix IV PCI Express IP core to all 0s?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

For normal operation you cannot set test_in ports to all 0s.

Please set the following test_in inputs to 1:
   bit[3] = FPGA mode.
   bit[5] = When set, prevents the LTSSM from entering compliance mode.
   bit[7] = Disables low power state negotiation.

Related Products

This article applies to 5 products

Cyclone® IV GX FPGA
Stratix® IV GT FPGA
Stratix® IV GX FPGA
Arria® II GX FPGA
Arria® II GZ FPGA

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