Article ID: 000085606 Content Type: Troubleshooting Last Reviewed: 07/24/2013

Does the source synchronous SERDES support data rates up to 1600Mbps for all serialization and deserialization factors in Stratix IV devices?

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Description

The maximum possible data rate achieved in the Stratix® IV device source synchronous SERDES is design dependent.  The source synchronous SERDES is implemented by using the ALTLVDS_RX and ALTLVDS_TX megafunctions.  You can select the deserialization / serialization factor for your interface using these megafunctions.  

 

The Fmax specification for the SERDES is based on the fast clock used for the serial data.  The interface Fmax is also dependent on the parallel clock domain which is design dependent and requires timing analysis.

 

Higher deserialization / serialization factors results in a slower parallel clock domain operation which allows timing closure for high data rate interfaces. 

 

Related Products

This article applies to 3 products

Stratix® IV E FPGA
Stratix® IV GT FPGA
Stratix® IV GX FPGA

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