Article ID: 000085582 Content Type: Troubleshooting Last Reviewed: 08/29/2013

What is the Tskew for Stratix Enhanced PLLs for different E clock outputs with the same counter values?

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Description The Stratix handbook version 3.1, Sep 2004 specifies /- 75 ps maximum skew for Enhanced PLLs using different E clock outputs with the same counter settings. This value can be specified since the clock outputs will have the same phase relationship. This specification also applies to output clocks with the same integer multiplier (I.E. 100 MHz and 200 MHz clocks) because they have the same phase relationship.

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Stratix® FPGAs

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