Article ID: 000085420 Content Type: Error Messages Last Reviewed: 09/11/2012

Error: Output port OUTCLK of stratixv_phy_clkbuf atom "Hierarchy|{instance_name}_p0_memphy_top:memphy_top_inst|uphy_clkbuf_memphy" has one or more illegal fan-outs.


  • Quartus® II Subscription Edition

    You may get this error along with the following error when compiling DDR3 SDRAM UniPHY based controller generated for Stratix® V device in Quartus® II software version 11.0 or earlier in Quartus II software version 11.0SP1.

    Error: The stratixv_clkena Atom "Hierarchy|{instance_name}_p0_memphy_top:memphy_top_inst|pll_write_clk~CLKENA0" is an illegal destination

    This error occurs due to the following global signal assignment made in QSF file for pll_write_clk signal

    set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to "Hierarchy|{instance_name}|pll_write_clk"

    This assignment is made by the version of the IP before 11.0SP1 and is present in the QSF when you move to Quartus II version 11.0SP1 which puts this clock on PHY clock tree instead of global clock tree that was used in the version before it.


    To fix this issue, comment out any global signal assignments made to pll_write_clk signal in your QSF file or run the {instance_name}_pin_assignments.tcl file in Quartus II software version 11.0SP1 after regenerating the core.

    Related Products

    This article applies to 4 products

    Stratix® V E FPGA
    Stratix® V GT FPGA
    Stratix® V GS FPGA
    Stratix® V GX FPGA