Article ID: 000085388 Content Type: Troubleshooting Last Reviewed: 03/13/2014

Info (332171): The following clock uncertainty values are less than the recommended values that would be applied by the derive_clock_uncertainty command

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Information messages regarding clock uncertainty may be seen in some UniPHY IP applications.

Info (332171): The following clock uncertainty values are less than the recommended values that would be applied by the derive_clock_uncertainty command
    Info (332172): Setup clock transfer from mem_cq_n[0] (Rise) to if0|pll0|pll_afi_clk (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.090

The reason for these messages is that in this particular case, the clock uncertainties are intentionally zero-ed out because they are already included elsewhere in the timing analyis. 

Resolution

It is recommended to search for the affected clock in the UniPHY IP SDC file and verify that statements are observed of the type :

# Clock Uncertainty is accounted for by the ...pathjitter parameters

  set_clock_uncertainty -from [ get_clocks ] 0
  set_clock_uncertainty -to [ get_clocks ] 0  

These Info messages can be safely ignored.

 

Related Products

This article applies to 4 products

Stratix® V GX FPGA
Stratix® V GT FPGA
Stratix® V GS FPGA
Stratix® V E FPGA

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