Article ID: 000085376 Content Type: Error Messages Last Reviewed: 06/18/2012

Warning Message Displayed When Driving User Logic with Custom PLL in Hard Memory Interface


  • Quartus® II Subscription Edition
  • PLL

    Critical Issue


    This problem affects DDR2 and DDR3 products.

    External memory interfaces targeting Arria V or Cyclone V devices and using the hard memory controller will generate warning messages if you drive user logic with a PLL other than the AFI clock.

    The following warning messages are displayed (where SingleInterface_mem_if_ddr3_emif_0. is a user-specified name):

    Critical Warning: SingleInterface_mem_if_ddr3_emif_0_p0_pin_map.tcl: Failed to find PLL clock for pins Warning: SingleInterface_mem_if_ddr3_emif_0_p0_pin_map.tcl: Could not find all DRIVER CORE CK pins


    The workaround for this issue is as follows:

    1. Open the pin-mapping script in a text editor.
    2. In the pin-mapping script, locate the following lines:
    if {[get_collection_size [get_registers -nowarn (driver_core_ck_pins)]] > 0} { �

    Replace the above lines with the following:

    if {[string compare -nocase (driver_core_ck_pins) ""] != 0 && [get_collection_size [get_registers -nowarn (driver_core_ck_pins)]] > 0} {

    • In the SDC file, change the pll_driver_core_clock to the clock that drives the user logic.
    • This issue will be fixed in a future version.

    Related Products

    This article applies to 2 products

    Cyclone® V FPGAs and SoC FPGAs
    Arria® V FPGAs and SoC FPGAs