Article ID: 000085374 Content Type: Troubleshooting Last Reviewed: 01/13/2014

What is the maximum operating frequency for an external memory interface using the custom PHY?

Environment

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    Description The supported maximum global clock network frequency specification is 717 MHz for the fastest speed grade Stratix® V devices. Therefore, the maximum achievable frequence for a custom external memory interface using a custom PHY and the global clock network is 717MHz. 
    Resolution

    To create an interface running at a frequency higher than 717 MHz, use the UniPHY-based memory controllers. They utilize the PHY clock (PHYCLK) network, which can operate up to 800 MHz.

    For more information on the PHYCLK network, refer to the External Memory Interfaces in Stratix V Devices chapter in volume 2 of the Stratix V Device Handbook.

    Related Products

    This article applies to 4 products

    Stratix® V E FPGA
    Stratix® V GS FPGA
    Stratix® V GT FPGA
    Stratix® V GX FPGA

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