Article ID: 000085373 Content Type: Troubleshooting Last Reviewed: 02/14/2012

Designs with Error Correction Coding (ECC) Do Not Work After Subsequent Reset

Environment

    Quartus® II Subscription Edition
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Critical Issue

Description

Some designs with ALTMEMPHY-based DDR, DDR2, or DDR3 SDRAM high-performance controllers do not work with the Enable Error Detection and Correction Logic option turned on.

This issue affects all designs that use DDR, DDR2, or DDR3 SDRAM high-performance controllers with the Enable Error Detection and Correction Logic option turned on.

Your design does not work properly in both simulation and hardware after the subsequent reset.

Resolution

None.

This issue will be fixed in a future version.

Related Products

This article applies to 1 products

Intel® Programmable Devices

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