Article ID: 000085345 Content Type: Troubleshooting Last Reviewed: 08/27/2013

Is the VCO post-scale bit in the memory initialization file (MIF) generated by Quartus II software for Stratix III PLL reconfiguration being set incorrectly?


  • Quartus® II Subscription Edition

    Yes, the VCO post-scale bit in the MIF generated by Quartus® II software versions 7.2SP3 and prior, for Stratix® III PLL reconfiguration, is being set incorrectly.
    This is bit 9 in the MIF and this bit setting determines if the VCO post scale counter (K) is bypassed or not.

    The Quartus II Assembler sets this bit to '1' if bypassing the VCO post-scale counter, which is correct for Stratix III devices. The MIF writer is setting the bit to '0' which is incorrect for Stratix III devices.

    The Quartus II Assembler which generates the device configuration file sets the bit correctly.  The PLL will operate as designed prior to PLL reconfiguration in user mode operation.  This issue only affects the MIF generated for PLL reconfiguration.  To ensure proper operation after PLL reconfiguration, you will need to manually edit the MIF and change bit 9 to the correct setting.

     The handbook will also be updated in a future revision.

    Resolution The MIF writer is fixed the Quartus II software version 13.0.

    Related Products

    This article applies to 1 products

    Stratix® III FPGAs