Article ID: 000085337 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why is there a shift in the common mode voltage level of the negative pin of Differential SSTL or HSTL input with Parallel OCT enabled in Stratix III and Stratix IV devices ?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The Quartus® II software versions 8.1 and 9.0 incorrectly disable Parallel OCT on the negative pin of a differential input. This problem occurs when using differential IO standards SSTL or HSTL even with Parallel OCT enabled.

This problem affects only Stratix® III and Stratix IV devices.

To fix this problem in the Quartus II software version 8.1 or 9.0, download and install one of the following patches:

Quartus II 8.1 Patch 0.55 for PC

Quartus II 8.1 Patch 0.55 for PC readme.txt

Quartus II 8.1 Patch 0.55 for Linux

Quartus II 8.1 Patch 0.55 for Linux readme.txt

 

Quartus II 9.0 Patch 0.03 for PC

Quartus II 9.0 Patch 0.03 for PC readme.txt

Quartus II 9.0 Patch 0.03 for Linux

Quartus II 9.0 Patch 0.03 for Linux readme.txt

This problem is scheduled to be fixed in a future version of the Quartus II software.

Related Products

This article applies to 1 products

Stratix® III FPGAs

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