Article ID: 000085316 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why is the power estimate for my design with clock enables turned off almost the same magnitude of the power estimate with all clocks enabled?



For core and IO registers, disabling the clock enable (CE) will prevent the registers from toggling but the clock tree will continue to toggle, consuming power.  Because the clock tree is a large source of power consumption (much larger than the registers they toggle), you should expect, on average, only a moderate change in power consumption after registers have their CEs disabled.  However, by using clock enables you prevent the outputs from the blocks to toggle so you also save the dynamic power associated with toggling the routing unnecessarily or any downstream combinational logic fed by the block in question. 

For RAM blocks, most of their power comes from clocking the RAM and when you do not clock the RAM it consumes negligible amounts of power.  Therefore, you may see a more noticeable difference when using clock enables on RAMs.

In summary, each design is unique and while some designs will not benefit as tremendously from use of clock enables as others, Altera recommends that you use CEs and gauge their effectiveness for your design.

While this solution can help explain the behavior of two identical designs with CEs on and CEs off, this is not meant to be specification or recommendation of power for your particular design.  In all cases, ensure you simulate your power to predict the power consumption that is specific to your chip.

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