There is a problem with the RTL simulation of the dynamic phase step feature for Cyclone® III devices when using VHDL. The phase step shown in the RTL simulation may not match the expected phase shift. The phase shift resolution is deterministic, it is 1/8th the VCO period.
This issue affects the Quartus® II software versions beginning in 9.1.
This problem does not affect VHDL gate level simulation, Verilog RTL simulation, or Verilog gate level simulation.
To work around this issue, you can turn on the Create output file(s) using the \'Advanced\' PLL parameters option in the ALTPLL MegaWizard™ Plug-in Manager. This option is on the "Inputs/Lock" page of the megafunction. For more information on this option, refer to the ALTPLL Megafunction User Guide (PDF).