Article ID: 000085291 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why are the dynamic phase steps not matching the phase shift resolution in RTL simulation for Cyclone III devices?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    There is a problem with the RTL simulation of the dynamic phase step feature for Cyclone® III devices when using VHDL.  The phase step shown in the RTL simulation may not match the expected phase shift.  The phase shift resolution is deterministic, it is 1/8th the VCO period. 

    This issue affects the Quartus® II software versions beginning in 9.1.

    This problem does not affect VHDL gate level simulation, Verilog RTL simulation, or Verilog gate level simulation.

    Resolution

    To work around this issue, you can turn on the Create output file(s) using the \'Advanced\' PLL parameters option in the ALTPLL MegaWizard™ Plug-in Manager.  This option is on the "Inputs/Lock" page of the megafunction.  For more information on this option, refer to the ALTPLL Megafunction User Guide (PDF).

    Related Products

    This article applies to 2 products

    Cyclone® III LS FPGA
    Cyclone® III FPGAs

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