Article ID: 000085285 Content Type: Error Messages Last Reviewed: 04/30/2014

Error: pcie_av_hip_de_hip_status_0: wrong # args: should be "proc_quartus_synth name"

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

This error will be seen when generating a testbench for the PCI Express® reference design supplied with AN456 in either Arria® V or Cyclone® V devices. This error is due to the Status Output Bridge module not having a suitable simulation model.

Qsys will reports the following error if you generate the testbench with these settings:
- Create testbench Qsys system: Standard, BFMs for standard Avalon interfaces
- Create simulation Model : Verilog

Error: pcie_av_hip_de_hip_status_0: wrong # args: should be "proc_quartus_synth name"
    while executing
"proc_quartus_synth"
    (procedure "proc_sim_verilog" line 2)
    invoked from within
"proc_sim_verilog altpcie_av_hip_ast_hip_status_bridge"
Info: pcie_av_hip_de_hip_status_0: "top" instantiated altera_pcie_av_hip_de_hip_status "pcie_av_hip_de_hip_status_0"
Error: Generation stopped, 3 or more modules remaining
Info: top: Done top" with 7 modules, 89 files, 3559773 bytes
Error: ip-generate failed with exit code 1: 2 Errors, 8 Warnings

Resolution

For simulation, either remove the status module from the design or use another sample design available from your Quartus® II installation directory.
<your installation directory>\ip\altera\altera_pcie\...

Related Products

This article applies to 4 products

Cyclone® V GT FPGA
Arria® V GT FPGA
Cyclone® V GX FPGA
Arria® V GX FPGA

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