Article ID: 000085443 Content Type: Error Messages Last Reviewed: 05/06/2014

Error: pcie_sv_hip_de_hip_status_0: wrong # args: should be "proc_quartus_synth name"

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

When recompiling the PCI Express® reference design supplied with AN465 the following error occurs:

Error: pcie_sv_hip_de_hip_status_0: wrong # args: should be "proc_quartus_synth name"
    while executing
"proc_quartus_synth"
    (procedure "proc_sim_verilog" line 2)
    invoked from within
"proc_sim_verilog altpcie_sv_hip_ast_hip_status_bridge"?

This error relates to the gasket Application Layer logic that drives LEDs on the PCB. It is not required when creating a full PCIe design. You may remove the Qsys element and have no loss of functionality.

Resolution Remove Qsys component pcie_sv_hip_de_hip_status_0.

Related Products

This article applies to 13 products

Stratix® V GX FPGA
Cyclone® V ST SoC FPGA
Cyclone® V SX SoC FPGA
Stratix® V GS FPGA
Stratix® V GT FPGA
Cyclone® V GX FPGA
Cyclone® V SE SoC FPGA
Cyclone® V GT FPGA
Arria® V SX SoC FPGA
Arria® V ST SoC FPGA
Arria® V GX FPGA
Arria® V GZ FPGA
Arria® V GT FPGA

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