When recompiling the PCI Express® reference design supplied with AN465 the following error occurs:
Error: pcie_sv_hip_de_hip_status_0: wrong # args: should be "proc_quartus_synth name"
(procedure "proc_sim_verilog" line 2)
invoked from within
This error relates to the gasket Application Layer logic that drives LEDs on the PCB. It is not required when creating a full PCIe design. You may remove the Qsys element and have no loss of functionality.