Article ID: 000085217 Content Type: Product Information & Documentation Last Reviewed: 08/13/2012

How can I share a single On-Chip Termination (OCT) calibration block with different I/O pins that each have different termination values in Stratix III or Stratix IV devices?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

To share a single On-Chip Termination (OCT) calibration block with different I/O pins each having different termination values (50 ohm and 25 ohm) in Stratix® III and Stratix IV devices, you must use the ALTIOBUF megafunction for the I/O pins that uses 25-Ohm series termination with calibration.  

In order to use the same termination block for both 50 ohm and 25 ohm calibrated OCT, the I/O pins must share the same VCCIO voltage.  

Beginning with Quartus II software version 9.0, the ALTIOBUF megafunction allows you to choose "Use left shift series termination control" which allows a calibrated 50 ohm termination block to achieve a 25 ohm output impedance for that output or bidirectional pin. 

Prior to Quartus II software version 9.0, you will need to add a WYSIWYG parameter to the ALTIOBUF instance.

For example, assume you require an input pin with 50-Ohm parallel termination with calibration operating as an SSTL 1.8 Class II input and an output pin with 25-Ohm series termination with calibration operating as an SSTL 1.8 Class II output, located in the same bank or in different banks (with the same VCCIO). To facilitate this, perform the following :

  • Assign an ALTIOBUF megafunction in output mode between the output pin and the internal signal that feeds that pin.
  • Open the generated ALTIOBUF Verilog or VHDL file and add the following defparam (Verilog) or Generic Map parameter (VHDL)
    • obufa_0.shift_series_termination_control = "true", (VERILOG)
    • shift_series_termination_control => "true", (VHDL)
  • Assign 25-Ohm Series OCT with Calibration to that output pin.
  • Compilation of the design will result in one calibration block being used (i.e. one pair of RUP /RDN pins).
  • You need to connect these RUP and RDN pins to VCCIO and GND via a 50-Ohm resistor respectively. The 25 Ohm series termination will be derived by a divide by two function.

More information on the ALTIOBUF megafunction can be found in the I/O Buffer Megafunction (ALTIOBUF) User Guide (PDF).

Related Products

This article applies to 4 products

Stratix® IV GT FPGA
Stratix® III FPGAs
Stratix® IV E FPGA
Stratix® IV GX FPGA

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