Article ID: 000085200 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Is there an issue with device migration in Cyclone IV devices when implementing DDR SDRAM or DDR2 SDRAM interface with ALTMEMPHY based controller?

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Description

Yes, there is an issue with device migration in Cyclone® IV devices when implementing DDR SDRAM or DDR2 SDRAM interface with ALTMEMPHY based controller.

Assigning the mem_clk[0] pin on the same row or column pad group as the DQ pins is not allowed in Cyclone IV devices. If you have turned on device migration, Quartus® II software only checks the pin-out rules regarding memory interface mem_clk pin placement for the main device and will not check for the migration device that is selected in the software. So you might be failing to comply with this rule for migration device but Quartus II software will not report this.

More information on this pin-out rule is given in External Memory Interface Handbook Volume 2, Section I Device and Pin Planning (PDF)

As a workaround, compile the design for the main device and the migration device seperately to check for the pin-out rule check for both devices.

The issue is present in Quartus II software version 10.1SP1 and earlier. The issue will be fixed in the future version of the software.

Related Products

This article applies to 3 products

Cyclone® III FPGAs
Cyclone® IV E FPGA
Cyclone® IV GX FPGA

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