Article ID: 000085755 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Are there any known issues with mem_clk placement in Cyclone III devices?

Environment

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Description

When implementing the DDR and DDR2 SDRAM High Performance Controller in Cyclone® III devices in Quartus® II software version 9.0SP2 and earlier, if the mem_clk signals (CK, CK#) are placed incorrectly, fitter and Timequest warnings or critical warnings will be seen.

 

Altera’s guidelines in the Cyclone III External Memory Interface chapter currently state : 

 

CK/CK# pins must be placed on differential I/O pins and cannot be placed on the same row or column as the DQ pins.

 

To meet the guidelines and achieve a correctly constrained design, mem_clk signals in Cyclone III devices must be placed on pins that meet these requirements:

 

- A Differential IO pin pair (identified as DIFFIO in Pin Planner).

- In the same bank or on the same side as the data pins. You can use either side of the device for wraparound interfaces.

 

- Must not use PLL CLKOUT pins (identified as L in Pin Planner)

 

- As seen in the Pin Planner Pad View, mem_clk[0] must not be located in the same row/column pad group as any of the interfacing DQ pins.

 

Check your design to ensure there are no critical warnings.

 

Not adhering to these rules may result in the failure to constrain the DDIO input nodes correctly and close timing. In addition, the Read Capture and Write timing margins computed by Time Quest may not be valid.

 

The following diagrams show examples of incorrect and correct mem_clk pin location assignments:

 

Incorrect Assignment

Incorrect Assignment;

Correct Assignment

Correct Assignment

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