Cyclone® V FPGA transceiver banks are grouped and named differently than Stratix® V or Arria® V devices.
The Cyclone V transceiver banks consist of 3 transceivers per bank rather than the 6 that are found in Stratix V and Arria V devices. Internal Cycone V clocking including x6 and xN clock networks are similar to the Stratix V and Arria V devices. The additional transceiver banks in Cyclone V are confined to a difference in name only.
Some earlier versions of the Cyclone V Handbook may show 6 transceivers per bank but this is incorrect and will be updated in a future release. Quartus® II already reflects this name change as shown in the Pin Planner, output reports, etc., and pinout spreadsheets available on the Altera website also reflect this name change.