Article ID: 000085185 Content Type: Troubleshooting Last Reviewed: 10/08/2015

Why do my transactions through the Arria 10 light weight axi interface function incorrectly in hardware?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description Due to a problem in the auto generated timing constraints in the Quartus® II software versions 15.0 update 2 and earlier, paths through the Arria® 10 light weight AXI interface are not correctly timing analysed which  could lead to functional problems in hardware.
Resolution

To avoid this issue comment out the following timing assignments from the *altera_arria10_interface_generator*.sdc file.

set_false_path -through [ get_pins -compatibility_mode *fpga_interfaces|hps2fpga_light_weight*aw_ready]
set_false_path -through [ get_pins -compatibility_mode *fpga_interfaces|hps2fpga_light_weight*aw_valid]
set_false_path -through [ get_pins -compatibility_mode *fpga_interfaces|hps2fpga_light_weight*w_ready]
set_false_path -through [ get_pins -compatibility_mode *fpga_interfaces|hps2fpga_light_weight*w_valid]
set_false_path -through [ get_pins -compatibility_mode *fpga_interfaces|hps2fpga_light_weight*ar_ready]
set_false_path -through [ get_pins -compatibility_mode *fpga_interfaces|hps2fpga_light_weight*ar_valid]

This problem is scheduled to be resolved in a future release of the Quartus II software.

Related Products

This article applies to 3 products

Intel® Arria® 10 SX SoC FPGA
Intel® Arria® 10 GX FPGA
Intel® Arria® 10 GT FPGA

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.