Article ID: 000085162 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why does the TimeQuest timing analyzer generate incorrect PLL output clock frequencies after running the derive_pll_clocks command?

Environment

    Quartus® II Subscription Edition
    PLL
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Description

Due to a problem in the Quartus® II software version 11.1 SP2 and earlier, the derive_pll_clocks command in the TimeQuest timing analyzer may generate clocks with incorrect frequencies for certain PLL configurations. This problem affects designs targeting Arria® V, Cyclone® V and Stratix® V devices.

If the derive_pll_clocks command is used with the -create_base_clocks option, the input clock frequency may be half the correct frequency. If the input clock has been defined by the user, the PLL output clocks may be double the correct frequency.

This problem affects timing analysis only. The PLL implemented on the device has the correct multiplication or division factors.

Resolution

If your PLL implementation has the problem described, constrain your PLL clocks manually. Replace the derive_pll_clocks command with create_clock and create_generated_clock commands.

This problem is fixed beginning with the Quartus II software version 12.0.

Related Products

This article applies to 14 products

Cyclone® V SX SoC FPGA
Cyclone® V GT FPGA
Stratix® V GX FPGA
Cyclone® V GX FPGA
Stratix® V GT FPGA
Stratix® V GS FPGA
Arria® V SX SoC FPGA
Cyclone® V ST SoC FPGA
Arria® V ST SoC FPGA
Arria® V GX FPGA
Arria® V GT FPGA
Cyclone® V E FPGA
Stratix® V E FPGA
Cyclone® V SE SoC FPGA

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