Article ID: 000085148 Content Type: Product Information & Documentation Last Reviewed: 09/11/2012

How can I configure the Stratix® II GX transceiver channel to run between 2Gbps-3.125 Gbps data rate using 'BASIC - double width' mode



In the Quartus® II software version 6.1 and 7.0, you cannot configure the ALT2GXB Megawizard® Plug-in Manager in BASIC mode(with deserializer block width set to double width ) at data rates in the 2.5Gbps-3.125Gbps and 2Gbps-3.125Gbps range  for configuration1 and configuration2 mentioned below.

configuration1: PLD interface width=16, 8B/10B and rate matcher are used.

configuration2: PLD interface width=16, no 8b/10b, no rate matcher and no byte ordering block.

The reason for this data rate restriction is that in version 6.1, the ALT2GXB Megawizard allows a maximum data rate  of  5Gbps and 4Gbps for configuration 1 and configuration 2 respectively. When you use the '/2' option in the 'data rate division factor'(in the 'General' screen of the ALT2GXB Megawizard), you can achieve the effective data rate of up to only 2.5Gbps for configuration1 and 2Gbps for configuration2.

This restriction is fixed beginning with the Quartus II software version 7.1. 

Therefore to run the transceiver up to 3.125Gbps data rate in the above mentioned configurations, use the Megawizard with the allowed data rate and then manually change the following parameters in the output .v/.vhd files generated by the ALT2GXB Megawizard.





The following example shows the required modification to get the effective data rate of 3Gbps for configuration1,  for a verilog file generated by the ALT2GXB Megawizard.

Step1: Set the ALT2GXB megawizard in configuration1. Set the reference clock input frequency to 125MHz. Set the data rate to 5Gbps. Set the 'data rate division factor' to 2.  As per this setting, the transceiver runs at 2.5Gbps.

The generated .v  has the following parameter values.

alt2gxb_component.cmu_pll_inclock_period = 8000

alt2gxb_component.rx_cru_inclock_period =8000

alt2gxb_component.rx_data_rate = 5000

alt2gxb.component.tx_data_rate =5000

Step 2: Edit the above .v file.  You have used 125MHz (5Gbps =125*40) in step 1.  To get the maximum data rate of 6Gbps you should change the input reference clock frequency to 150MHz (150*40 = 6Gbps). Since you have used the 'data rate division factor' of 2 in step 1, you get the 3Gbps effective data rate. The following are the required changes in the .v file.

 alt2gxb_component.cmu_pll_inclock_period = 6667

alt2gxb_component.rx_cru_inclock_period =6667

alt2gxb_component.rx_data_rate = 6000

alt2gxb.component.tx_data_rate =6000

--For Functional verilog RTL simulation in third party tools, change the following parameters in the .vo file.






For this example, change the values for the above parameters to 6667 (to reflect 150MHz input reference clock).

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This article applies to 1 products

Stratix® II GX FPGA