Article ID: 000085048 Content Type: Product Information & Documentation Last Reviewed: 01/21/2015

How do I implement and connect between an external Altera_PLL and an ALTLVDS_RX with Dynamic Phase Alignment (DPA) enabled?

Environment

  • Arria® V GT FPGA
  • Stratix® V E FPGA
  • Arria® V ST SoC FPGA
  • Arria® V GX FPGA
  • Stratix® V GX FPGA
  • Arria® V GZ FPGA
  • Arria® V SX SoC FPGA
  • Stratix® V GS FPGA
  • Stratix® V GT FPGA
  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    When using ALTLVDS_RX in external PLL mode with DPA enabled in Quartus® II software versions 12.1 and later, you will receive an error in Analysis and Synthesis as shown below:

    Error: SERDES DPA Block node \'lvds_rx:lvds_rx_inst0|altlvds_rx:ALTLVDS_RX_component|lvds_rx_lvds_rx:auto_generated|lvds_rx_dpa3\' is not properly connected on the \'DPACLKIN\' port. It must be connected to one of the valid ports listed below.
        Info: Can be connected to PHOUT port of arriav_pll_dpa_output WYSIWYG
        Info: Can be connected to OUTCLK port of generic_pll WYSIWYG

    This affects Arria® V and Stratix® V devices.

    Modify your design when using the ALTLVDS_RX megafunction in external PLL mode with DPA enabled by downloading this How-to document and example-project.zip file. 

    First, you must complete the steps for implementing ALTLVDS_RX and ALTLVDS_TX with external PLL mode as described in the related solution below.

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.