When using ALTLVDS_RX in external PLL mode with DPA enabled in Quartus® II software versions 12.1 and later, you will receive an error in Analysis and Synthesis as shown below:
Error: SERDES DPA Block node \'lvds_rx:lvds_rx_inst0|altlvds_rx:ALTLVDS_RX_component|lvds_rx_lvds_rx:auto_generated|lvds_rx_dpa3\' is not properly connected on the \'DPACLKIN\' port. It must be connected to one of the valid ports listed below.
Info: Can be connected to PHOUT port of arriav_pll_dpa_output WYSIWYG
Info: Can be connected to OUTCLK port of generic_pll WYSIWYG
This affects Arria® V and Stratix® V devices.
First, you must complete the steps for implementing ALTLVDS_RX and ALTLVDS_TX with external PLL mode as described in the related solution below.