Article ID: 000078606 Content Type: Error Messages Last Reviewed: 08/08/2023

Error (10228): Verilog HDL error at lvds_rx_lvds_rx.v(49): module "lvds_rx_accum" cannot be declared more than once


  • Quartus® II Subscription Edition

    You may see this error in the Quartus® II software versions 13.1 and later when implementing the ALTLVDS_RX IP with external Altera_PLL and Dynamic Phase Alignment (DPA) enabled with more than two channels in Arria® V devices. 


    To work around this, first, complete the steps for implementing ALTLVDS_RX and ALTLVDS_TX with external PLL mode as described in the related solutions.

    Then, after running Analysis and Synthesis in the Quartus II software, copy the lvds_rx_lvds_rx module from the contents of the file db/lvds_rx_lvds_rx.v into the lvds_rx.v file.
    This will add the module lvds_rx_lvds_rx into the lvds_rx.v file.

    Ensure all occurrences of rx_dpaclock is 8 bits and all connections of rx_dpaclock are correct.

    For example,
    instead of:

    Related Products

    This article applies to 6 products

    Arria® V FPGAs and SoC FPGAs
    Arria® V GT FPGA
    Arria® V ST SoC FPGA
    Arria® V GX FPGA
    Arria® V GZ FPGA
    Arria® V SX SoC FPGA