Article ID: 000084996 Content Type: Troubleshooting Last Reviewed: 10/01/2013

Cyclone IV Device Family Pin Connection Guidelines: Known Issues



Issue 137246: Version 1.5

If the JTAG connections are not used, you need to connect the TCK to GND, TDI and TMS pin to VCCA, and leave TDO unconnected. 

Issue 77849: Version 1.4

Cyclone IV E devices does not have dedicated clock pin CLK0. Up to 15 dedicate clock pins (CLK[15..1]) are provided.

Issue 59732: Version 1.4

DATA0 and DATA1 are stated as being "Bidirectional open-drain" but this is incorrect and will be corrected to state that they are only "Bidirectional".

Issue 382585, Version 1.4

Note 2 does not list all of the available VCC_CLKIN voltages for banks 3B and 8B.  Version 1.4 lists only 2.5V, but 1.2V, 1.5V, 1.8V, 2.5V, 3.0V, and 3.3V are all supported voltages for VCC_CLKIN on banks 3B and 8B. 

Issue 66844, Version 1.4

For the CRC_ERROR pin Note 24 will be removed since it has no relation to the CRC_ERROR pin.

The pin description will also be updated to reflect that the CRC_ERROR pin is always an open-drain pin if used as a CRC_ERROR pin and it is not a dedicated output where you can enable the CRC_ERROR pin as an open-drain in the CRC_ERROR Detection tab of the Device and Pin Options dialog box.

Related Products

This article applies to 2 products

Cyclone® IV E FPGA
Cyclone® IV GX FPGA