Article ID: 000084923 Content Type: Product Information & Documentation Last Reviewed: 01/21/2015

How do I run SerialLite III streaming mode simulation for advanced clocking mode?


  • Quartus® II Subscription Edition

    The SerialLite III testbench example design generated with the IP core uses standard clocking mode (SCM) and default parameter settings. To run simulation in advanced clocking mode (ACM), the default settings in the testbench need to be modified manually to match the user settings in the IP parameter editor GUI. 


    1. Navigate to the \'<ip variation name>_example/seriallite_iii/example_testbench\' directory and open \'test_env.v\' file in a text editor.

    2. Modify the following test_env parameters to match the user IP parameter editor settings.
        - user_clock_frequency (Required user clock frequency)
        - pll_ref_freq (Transceiver reference clock frequency)
        - pll_ref_var (Transceiver reference clock frequency)
        - data_rate (Transceiver data rate per lane)
        - meta_frame_length (Meta frame length)
        - ecc_enable (ECC Protection)

    Note the following test_env parameters are not used in advanced clocking mode and can be ignored.
        - reference_clock_frequency (fPLL reference clock frequency)
        - coreclkin_frequency (Core clock frequency)  

    3. Go to \'./vsim\' sub-directory and open \'\' file in a text editor.
        a. Add \' define ADVANCED_CLOCKING\' to vsim command option.
        b. Set the number of lanes in \'-G/test_env/lanes=\'.
               - Default number of lanes is set to 5.

    4. Run simulation according to the procedure described in the SerialLite III user guide.

    Related Products

    This article applies to 1 products

    Stratix® V GX FPGA