When you compile a design that contains an LVDS transceiver block and targets a HardCopy device, the Quartus II software displays a warning message similar to the following:
Critical Warning: The following clock transfers have
no clock uncertainty assignment. For more accurate results, apply
clock uncertainty assignments or use the derive_clock_uncertainty
You may safely ignore the warning message. When you verify the timing results in the TimeQuest timing analyzer, you will not see the critical warning in the timing report.
This issue affects all HardCopy designs that contain LVDS transceiver blocks.
This issue will be fixed in a future version of the Triple Speed Ethernet MegaCore function.